About the project
This fully funded PhD investigates low‑power, high‑reliability chiplet physical‑layer design in advanced CMOS/FinFET technologies, including transceiver optimisation, reliability‑aware subsystems, interposer development, and electrical characterisation. The project includes full physical design and ASIC tapeout of chiplet prototypes, supported by industry‑linked soclabs.
With recent advances in many areas of semiconductor devices, applications are placing significant strain on hardware, and the 50-year relentless improvements that CMOS scaling has offered are reaching their limits. Instead, industry is shifting toward heterogeneous integration, including chiplets, advanced 2.5D/3D packaging, application-specific accelerators, and novel memory technologies. Communications between chiplets is facilitated by high-speed protocols such as UCIe, bunch of wires (BoW), and CHI. Underpinning these communication protocols is the physical layer (or PHY), which handles the transmission and receival of data over the interconnects. The PHY layer can also handle reliability/performance optimisation of the transactions between chiplets by monitoring the quality of the transactions and adjusting parameters accordingly.
This PhD project will research the design and optimisation of chiplet physical layers in CMOS and/or FinFET technologies. This may include:
- design and optimisation of the serial transmitters and receivers, optimising for low power and area
- exploring monitoring and control subsystems in the PHY for reliability and performance optimisation
- physical design, tapeout and post-silicon characterisation of chiplets in finFET nodes
- design and optimisation of interposers for improved communication and offloading of components from the chiplets (e.g. passive components)
- electrical characterisation of interposers and chiplet systems
You will get to work on leading edge CMOS fabrication nodes and Chiplets with industry seasoned engineers as well as world leading research.
This PhD project will be done in collaboration with soclabs, a group at the University of Southampton working closely with industry leaders in semiconductor design including Arm and Synopsys. The soclabs team, including David Flynn (previously a fellow in R&D at Arm and with the company for over 25 years), will provide technical expertise and guidance throughout the project.
The School of Electronics & Computer Science is committed to promoting equality, diversity inclusivity as demonstrated by our Athena SWAN award. We welcome all applicants regardless of their gender, ethnicity, disability, sexual orientation or age, and will give full consideration to applicants seeking flexible working patterns and those who have taken a career break. The University has a generous maternity policy, onsite childcare facilities, and offers a range of benefits to help ensure employees’ well-being and work-life balance. The University of Southampton is committed to sustainability and has been awarded the Platinum EcoAward.
