Resilient and Testble Energy-Efficient Digital Hardware

The UK is home to some world-leading electronic companies including semiconductor IP supplier of low-power microprocessors (ARM), multimedia and communications cores (Imagination Technologies); which are at the heart of today's and future consumer electronics, and home entertainment. Power management is an essential enabling technology in such electronics and will become more prominent in future electronic systems. The downside of power management is that it decreases the reliability and increase the testability cost of energy-efficient hardware as demonstrated by recent academic and industrial research including that reported by the investigation team. This is because energy-efficient hardware often have no provision for tolerating run-time soft errors (unless for safety critical applications); and current methods for testing such hardware for manufacturing defects don't explicitly target power management circuitry. There are currently no fault models or test methods for power distribution networks and power management circuitry and no on-line soft error monitoring and correction methods for power management hardware. This grant application is focused on developing new fault models, methods, circuits and their validation (simulation, FPGA and AISC) to quantify and improve the resilience and testability of energy-efficient digital hardware. Particular emphasis is placed upon cost-effectiveness through joint consideration of reliability, and test and re-using on-chip hardware to minimise silicon area, power consumption and impact on functional performance. This is a three-year project involving two post-doctoral researchers (one for three years and the other for two years), and ARM (Cambridge) as an industrial partner. The project will be carried out in collaboration with Prof. F. Kurdahi (Uni. of California, Irvine) and Prof. M. Tehranipoor (Uni. of Connecticut). Both acknowledged world experts in the proposed research. This project will significantly advance the present state-of-the-art in reliable and testable energy-efficient hardware and will lead to the following research deliverables: 1. New fault models for power management circuitry and power distribution network (PDMC) to underpin their logic and timing behaviour due to soft errors and manufacturing defects; 2. New methods and circuits and their practical validation for improving testability and diagnosis (against manufacturing defects) and reliability (against soft errors) through online monitoring and correction. 3. A design automation methodology for embedding automatically into an energy-efficient design the required circuitry to enable enhanced reliability and testability using existing EDA tools.