Hardware Accelerators | AICE6005 | University of Southampton

Module overview

This module explores the use and programmability of field-programmable gate arrays (FPGAs) for accelerating data-intensive applications. They are usually found in the datacenter, high-performance computing (HPC) facilities, as well as high-end edge computing including in the automotive industry. Traditionally, FPGAs have mainly been a prototyping platform. The recent advances in semiconductor technology have enabled their use as a competitive accelerator platform in datacenters and on the edge. Their high flexibility can surpass the performance and efficiency of general-purpose processors, but this comes at a cost. When a task is able to be solved computationally, general-purpose computing is the easiest route due to the maturity of software and hardware stacks, but it may be too slow or inefficient. Would an acceleration platform like an FPGA or even a GPU be able to target the task effectively? Which algorithm would an FPGA solution use, and how could it benefit from its strengths such as the internal parallelism? Are there any programming models and programming languages for such data-intensive designs? This module covers the programmability aspects of FPGAs in the context of HPC and high-end edge devices. It covers the computer architecture of highly-heterogeneous SoCs and HPC systems, soft and hard interconnects relating to FPGA acceleration, and the steps required to develop and finally deploy data-intensive hardware accelerators.

Aims and Objectives

Learning Outcomes

Subject Specific Intellectual and Research Skills

Having successfully completed this module you will be able to:

Design and architect data-intensive FPGA-based solutions.
Select the best computational platform given a problem for acceleration, and predict the related trade-offs between the available options.
Apply parallel computing concepts such as dataflow and distributed algorithms, which extend beyond traditional parallel programming models and paradigms for CPUs and GPUs.

Knowledge and Understanding

Having successfully completed this module, you will be able to demonstrate knowledge and understanding of:

The heterogeneous system architectures prominent in datacenters, high-performance computing (HPC) and edge devices.
Field-programmable gate-arrays (FPGAs) as an acceleration platform, especially in data-intensive environments.
The strengths and weaknesses of High-Level Synthesis (HLS) to automate the generation of hardware modules using general-purpose programming languages.
The available options for hard and soft interconnects in high-performance computing accelerators.

Subject Specific Practical Skills

Having successfully completed this module you will be able to:

Implement accelerators using High-Level Synthesis.
Deploy and evaluate FPGA-based data-intensive accelerators as part of a larger system.

Transferable and Generic Skills

Having successfully completed this module you will be able to:

Architecting sustainability-conscious computing systems.

Syllabus

• Week 1-2: Field-Programmable Gate-Arrays as reconfigurable datacenter co-processors ◦ Reconfigurable Computing using Look-up Tables, Flip-Flops and Routing ◦ Heterogeneous Computer Architectures: Multi/many-Core Processors, Heterogeneous SoCs, AMD Versal, Heterogeneity in Memory ◦ Co-Processor Challenges: Offloading Paradigm, Interconnection Limitations, Portability, Programmability • Week 3-4: Advanced parallel programming models ◦ Horizontal and Vertical Parallelisation: Single Instruction-Multiple Data, Distributed Computing, Exploiting Wide Datapaths ◦ Dataflow Computing ◦ Distributed algorithms: Parallel Entities, Modular Design • Week 5-6: High-Level Synthesis ◦ Prominent Languages: Vivado HLS, OpenCL ◦ Relationship to Hardware Description Languages ◦ Expressiveness and Efficiency • Week 7-8: Deployment of Hardware Accelerators ◦ Host Code, Loading Bitstreams, Kernel Integration, Drivers/Userspace Drivers ◦ Virtual Instances with FPGAs in the Cloud: Amazon AWS EC2 F2, Microsoft Azure ◦ High-End Embedded SoCs: AMD/Intel MPSoCs • Week 9: Data-intensive workloads and algorithms ◦ Trending Workloads: Large-Language Models, Financial Computing, Quantum Algorithms and Big Data Analytics ◦ Impact of the Algorithms on System Behaviour: Compute-bound vs Memory-bound Execution, Memory Access Patterns, Cache Hierarchies and Communication • Week 10: Interconnection structures and technologies ◦ Hard Interconnects/ Protocols: PCI Express, AMBA AXI, Avalon, CCIX ◦ Soft Interconnects: Crossbar, Butterfly Network, Reverse Butterfly, Network-on-Chip, Permutation Network, Bus ◦ Applications in Silicon and Accelerators and Representativeness in Soft Logic • Week 11-12: Evaluation and characterisation of heterogeneous system performance ◦ Measuring Time: CPU-provided, FPGA-provided, Point of Measurement, Hardware Counters, PMU events ◦ Measuring Memory Footprint and Access Efficiency, Impact of Caching and Cache Coherency ◦ Performance and Energy Modelling and Profiling of Heterogeneous Systems ◦ (Student Project Presentations)

Learning and Teaching

Teaching and learning methods

• Lectures: Two hours per week during the teaching term • Labs: A 2-hour weekly drop-in session • Reading and preparation, including lecture notes and selected research papers.

Study time
Type	Hours
Completion of assessment task	50
Revision	14
Lecture	24
Wider reading or practice	36
Specialist Laboratory	48
Total study time	172

Resources & Reading list

Internet Resources

Digital Design with Chisel.

Vitis High-Level Synthesis User Guide (UG1399) v2025.1.

Textbooks

David J. Greaves (2021). Modern System-on-Chip Design on Arm. ARM.

Wim Vanderbauwhede, Khaled Benkrid et al. (2013). High-Performance Computing Using FPGAs. Springer Nature.

Nancy A. Lynch (1996). Distributed Algorithms. San Francisco, CA, USA: Morgan Kaufmann Publishers Inc..

William James Dally and Brian Patrick Towles (2004). Principles and practices of interconnection networks. The Morgan Kaufmann Series in Computer Architecture and Design.

Assessment

Assessment strategy

The coursework assessment will be of the form of an individual project. It will be divided into incremental parts for frequent feedback, also having a formative aspect. 40% of the coursework component (20% overall) will be based on an oral exam or presentation to verify the understanding of the submitted components in the era of LLMs, as well as to promote peer and more personalised feedback. Although the assignment will be well-structured, the students will be given an initial choice for the general theme of the task/algorithm to accelerate with the goal to differentiate the solutions and increase interest.

Summative

This is how we’ll formally assess what you have learned in this module.

Breakdown
Method	Percentage contribution
Individual Coursework	30%
Examination	50%
Oral presentation and a written assignment	20%